Feasibility and Performance Region Modeling of Analog and Digital Circuits

Hierarchy plays a signiicant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A vertical binary search technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. Macromodels have been developed and veriied for both analog and digital blocks. Analog macromodels have been developed at three diierent levels of hierarchy (current mirror, opamp, and A/D converter). The impact of diierent fabrication processes on the performance of analog circuits have also been explored. Though the modeling technique has been ne tuned to handle analog circuits the approach is general and is applicable to both analog and digital circuits. This feature makes it particularly suitable for mixed-signal designs.